The present invention related generally to the fabrication of complementary metal oxide semiconductor (CMOS) field effect transistors (FET), and more particularly, to a method for forming ultra-thin SOI (UTSOI) field effect transistors with stressed channel regions which provide increased carrier mobility among other benefits.
CMOS FETs are employed in almost every electronic circuit application such as signal processing, computing, and wireless communications. It has been demonstrated that ultra-thin SOI (UTSOI) FETs have a very good short channel control due to extremely thin channel region. Thin body devices however, lead to high series resistance Rext, which can be mitigated by forming raised source/drain (RSD) regions. It has also been demonstrated however, that thick channel SOI FETs exhibit improved FET performance such as switching speed and drive current, by applying stress in the channel. The improvement stems from enhanced carrier mobility in stressed FET channels.
Incorporating stress into UTSOI FETs is a challenge because of the thin channel region.
Commonly-owned, co-pending United States Patent Publication No. US20060175659A1 appears to describe a substrate having an UTSOI region and a bulk-Si region, and, in particular, forming of nFET and pFET devices on UTSOI.
Commonly-owned, co-pending United States Patent Publication No. US20050093021A1 describes a strained SiGe layer epitaxially grown on the Si body serving as a buried channel for holes, a Si layer epitaxially grown on the SiGe layer serving as a surface channel for electrons, and a source and a drain containing an epitaxially deposited, strained SiGe of opposing conductivity type than the Si body.
Commonly-owned U.S. Pat. No. 6,939,751 describes a (Raised Source Drain) RSD FET device with a recessed channel is formed with a raised silicon sources and drains and a gate electrode structure formed on an SOI structure (a Si layer formed on a substrate).
None of this prior art however, addresses the integration of an embedded pFET SiGe extension with raised source/drain regions.
It would thus be highly desirable to provide a method of making UTSOI CMOS devices where the PFET has an embedded SiGe extensions region and, where both NFETs and PFETs have raised source/drain structures.